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Diagnostic Bit Interval Timer

IP.com Disclosure Number: IPCOM000082689D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Dwire, JD: AUTHOR [+2]

Abstract

This timer provides for quantitatively evaluating the performance of a tape drive and provides a means of failure isolation when the timer is in diagnostic mode. In this mode, the performance is determined, based on time measurements of the serial data stream or "raw data: on line 10 derived from a magnetic tape read amplifier 12 and particularly based on parameters, such as tape average velocity, standard deviation from this average, minimum and maximum data cell times, and read channel peak shift.

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Diagnostic Bit Interval Timer

This timer provides for quantitatively evaluating the performance of a tape drive and provides a means of failure isolation when the timer is in diagnostic mode. In this mode, the performance is determined, based on time measurements of the serial data stream or "raw data: on line 10 derived from a magnetic tape read amplifier 12 and particularly based on parameters, such as tape average velocity, standard deviation from this average, minimum and maximum data cell times, and read channel peak shift.

Fig. 1 is a logic flow diagram for the hardware of the timer. Fig. 2 is a timing diagram for the logic in Fig. 1 and is divided into two sections to illustrate operation for the diagnostic test mode and operation in a normal read mode. When in normal read mode, the logic functions as a data clock separator. The circuit is under the control of the "diagnostic mode" signal on line 44. When signal 44 is up, the circuit is in diagnostic mode; and when the diagnostic mode signal 44 is down, the circuit is in read data mode, the signals for both of which are indicated in Fig. 2.

When in the normal read mode, the circuit interprets a raw data signal on line 10 and generates two new signals, namely, a "data" signal on line 27 and a read data gate clock signal on line 28. The data and read data gate signals can be fed into a data processor 30, with the read data gate signal 28 indicating the time when the processor 30 shall be responsive to the data indications in the data signal 27. The data signal 27 indicates whether a bit being thereby read by the data processor 30 is a 1 or is a 0.

A self-clocking F2F data signal such as from the output of a magnetic tape read amplifier 12 is shown in Fig. 2 as the raw data signal on line 10. This raw data signal is made up of clock pulses C spaced at regular intervals and data pulses D placed halfway between pairs of clock pulses C. The data pulses D are present only when a 1 bit exists in the raw data signal on line 10; and when a 0 bit is in the raw data signal on line 10, the data pulse D is missing.

It may be assumed that the clock time (the time between the clock pulses) in the raw data signal on line 10 is a fixed time t(c).

The circuit includes N-bit counter 14 feeding AND circuit 50. N-bit counter 14 is incremented in a counting action by the output of oscillator 16, until a pulse on the raw data line 10 passes through AND circuit 56, OR circuit 58 and AND circuit 60 to trigger the data shift sequence control 18 to provide a read data signal on line 22. This causes the read data gate signal on line 28 to exist, since the read data signal on line 22 passes through AND circuit 68 and OR circuit 70 to the line 28 under these conditions.

Following the raising of the read data signal on line 22, the sequence control 18 raises the "reset" signal on line 26, and the reset signal on line 26 resets N-bit counter 14 and also resets latches 36 and 40. At this time, N-bit counter...