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Display Refresh Buffer Addressing Technique

IP.com Disclosure Number: IPCOM000082746D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

In cathode-ray tube (CRT) display systems using a full vertical sweep raster, the CRT beam begins the display of a frame by sweeping the first column of dots for the first character on line 1, then the first column of dots for the first character on line 2, etc., until the first column of dots for the first character on each line has been displayed. After retrace, the beam sweeps the second column of dots for the first character on each line. During this time, the beginning characters on each line must be sequentially addressed in the display refresh buffer. Since some of the characters displayed may be wider than others, it may be necessary to address the second character on some lines while continuing to address the first character on other lines.

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Display Refresh Buffer Addressing Technique

In cathode-ray tube (CRT) display systems using a full vertical sweep raster, the CRT beam begins the display of a frame by sweeping the first column of dots for the first character on line 1, then the first column of dots for the first character on line 2, etc., until the first column of dots for the first character on each line has been displayed. After retrace, the beam sweeps the second column of dots for the first character on each line. During this time, the beginning characters on each line must be sequentially addressed in the display refresh buffer. Since some of the characters displayed may be wider than others, it may be necessary to address the second character on some lines while continuing to address the first character on other lines.

A series of shift registers 1-m, forming a loop configuration, are clocked to shift one revolution in synchronism with the display of a single column of character dots. The line begin addresses in the refresh memory are gated along line 10 through AND 11, through OR 12 and into address register 1 with the application of a positive LOAD signal on input line 7 of AND 11.

With the LOAD signal enabled, during successive clock times the line begin addresses of text display lines 2-m are similarly loaded into register 1, while previously loaded line begin addresses are shifted through delay circuit 13 back into address registers M, 5, 4, 3, and 2. An address register is provided, therefore, for each of the line begin addresses and delay 13, which may be an additional sequence of registers, adds a time delay equal to the retrace time o...