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Browse Prior Art Database

Time Sliced Microprogrammable I/O Controller

IP.com Disclosure Number: IPCOM000082754D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Irwin, JW: AUTHOR

Abstract

Microprogrammed subsystem functions are performed on a high-performance time-sliced microprocessor, operating with a plurality of control programs. Microprogrammed subsystem functions are performed on a high-performance Such programs have identical instruction execution times for maintaining program synchronization between the various programs. It is preferred that the programs are all completely reentrant.

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Time Sliced Microprogrammable I/O Controller

Microprogrammed subsystem functions are performed on a high- performance time-sliced microprocessor, operating with a plurality of control programs. Microprogrammed subsystem functions are performed on a high- performance Such programs have identical instruction execution times for maintaining program synchronization between the various programs. It is preferred that the programs are all completely reentrant.

In a preferred arrangement, two time-sliced microprocessors are in cascade arrangement between a controlling apparatus and one or more electromechanical devices, such as magnetic tape units and the like. A separate recording channel is connected between the recorders and the controlling apparatus for processing digital signals at high-data rates. The operation of the recording channel is supervised and jointly control led by the two microprocessors.

A typical time-sliced microprocessor is shown as having an ALU, and first and second instruction registers IA and IB, which are shifted through a delta adder for incrementing instruction word addresses. As shown, IB contains an instruction word to be executed by the ALU via a sequence control. During the next time slice, the memory address from IB is forwarded to the delta adder, while the instruction address from IA is transferred into IB for fetching an instruction in the alternate time slice. The microprocessor has a working store logically divided into SA and SB portions, respectively, for the first and second programs.

A common control store, which is accessed by either of the programs being executed, sequentially feeds instruction words to the sequence control as determined by the instruction word addresses from register IB. Branch instructions are executed by inserting a new instruction word address into the delta adder. Communication between the two microprocessors is via registers REG, which have internal connections not only from the sequence control, but from the working store and the ALU. External connections are made using known circuits and are sequenced by the sequence control with data path connections to the working store and the ALU, as is well known.

The logical configuration of the programs in the subsystem includes I-streams A1 and B1 for a first microprocessor and I-streams A2 and B2 for a second microprocessor, both of which are time sliced as above described. Working store portions SA1 and SB1 are used by the two I-streams A1 and B1, respectively, with I-streams A2 and B2 similarly sh...