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Parity Look Ahead

IP.com Disclosure Number: IPCOM000082756D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Deutch, JE: AUTHOR [+2]

Abstract

In some data processing apparatus, particularly of the encoding type, parity "look-ahead" (PA) of a string of 1's constitutes one encoding parameter. A PA generator provides this function. Such serial data is arranged in bytes. Accordingly, a byte PA generator (parity look-ahead for each received byte) generates predicted parity for serial data, as it is received and passed on to serial data processing circuits.

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Parity Look Ahead

In some data processing apparatus, particularly of the encoding type, parity "look-ahead" (PA) of a string of 1's constitutes one encoding parameter. A PA generator provides this function. Such serial data is arranged in bytes. Accordingly, a byte PA generator (parity look-ahead for each received byte) generates predicted parity for serial data, as it is received and passed on to serial data processing circuits.

A pair of registers receives the predicted parity and the parity bypass, as later discussed, for driving a PA data circuit, which provides predicted parity for strings of 1's in the next byte to be processed by the serial data processing circuits. Byte 1 is the current byte being processed, while bytes 2-N (N=16 in the example) are the bytes to be processed and on which parity is determined for each string of 1's.

The purpose of a PA generator is to take parity on a string of 1's anywhere in a data string irrespective of the length and location. Each time a 0 occurs, a new PA calculation is initiated, provided it is followed by a 1 as shown below: 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 1 1 1 1 0 * * * * * * * * * * = Start New PA

The described circuit generates parity on such strings of 1's irrespective of location and length for up to 128 bits (16 bytes).

The BYTE PA generator includes a series of eight AND circuits, one for each bit position in the byte. The AND's respond to two Positive inputs to supply a negative output. The last bit, or bit 7 of the byte, goes to the first AND circuit and is inverted if it is a binary 1; hence, the AND circuit for bit 6 is not enabled if bit 7 is a 1--it is enabled if it is a 0. If bit 6 is a 1 and bit 7 is a 0, then parity should be provided, i.e., binary 1; hence, a negative output signal is supplied.

The same logic can be followed through the AND circuit tree to generate an odd parity as a negative signal at the output labeled PA. This corresponds to a binary 1 parity signal or a carry-out from a group of bits. Both parity and bypass signals are stored in the two registers for use in the PA data circuit. The bypass signal in the BYTE PA generator is simply detecting all 1's in the eight bits, which in this case...