Browse Prior Art Database

Capacitor for Single FET Memory Cell

IP.com Disclosure Number: IPCOM000082773D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Clarke, GV: AUTHOR [+2]

Abstract

These single field-effect transistor (FET) memory cell structures use nonplanar capacitor plates to provide a reduction in cell area.

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Capacitor for Single FET Memory Cell

These single field-effect transistor (FET) memory cell structures use nonplanar capacitor plates to provide a reduction in cell area.

Fig. 1 is a sectional view of two single FET memory cells fabricated in silicon- on-insulator (SOI) technology. An insulating substrate 10 of, for example, sapphire is shown. The memory cells are of the type described in U. S. Patent 3,387,286 by R. H. Dennard, and include an FET comprising deposited N-type semiconductor regions 12 and 14 separated by P-type channel region 16. Region 12 extends on the surface of substrate 10 in a direction perpendicular to the plane of the paper and corresponds to a common bit-sense line for a plurality of memory cells, each cell associated with a separate word line.

Overlying regions 12, 14 and 16 is an insulating layer 18, which acts as a gate dielectric over region 16 for subsequently deposited word line conductor 20. Between the two transistors there is a conductive capacitor plate 22, of polycrystalline silicon for example, which is shared by adjacent memory cells. Plate 22 is capacitively coupled to regions 14 by insulation layer 18. Overlying the entire structure is a layer of thick insulation 24, through which word line 20 projects to form the gates of the transistors.

In view of the substantial vertical profile of the SOI transistor adjacent to capacitor plate 22, the surface area of substrate 10 required to form the memory capacitor is substantially re...