Browse Prior Art Database

Skew Insensitive AND Circuit

IP.com Disclosure Number: IPCOM000082774D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Delecki, JJ: AUTHOR [+2]

Abstract

This field-effect transistor (FET) AND circuit uses inversion capacitors to provide an input skew insensitive logic gate, capable of providing input signal levels on its output terminal.

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Skew Insensitive AND Circuit

This field-effect transistor (FET) AND circuit uses inversion capacitors to provide an input skew insensitive logic gate, capable of providing input signal levels on its output terminal.

The circuit includes isolation transistors T1 and T2 and switching transistors T3 and T4. Capacitors C1 and C2 are inversion capacitors having their fixed plate charged to VH-1 VT by devices T5 and T6. During standby input signals A and B are both at zero volts, VH is assumed to be 8.5 volts and the gates of T3 and T4 will be at about 6 volts, keeping T3 and T4 on and the output at zero volts.

If input A rises to 8.5 volts and input B remains at zero volts, T1 turns on pulling the gate of T3 to ground, turning T3 off. Since T4 remains on, any noise that is passed through T3 by input A is discharged by T4 into the zero potential on input B.

If input A and B rise simultaneously to 8.5 volts, the gates of T3 and T4 are bootstrapped via C1 and C2 up to about 15 volts turning both T3 and T4 on hard. The output rises to the input potential of 8.5 volts.

Assuming that the inputs A and B are both high but skewed with input A rising before input B, device T3 will turn off and when input B rises to 8.5 volts the output load will be driven up to 8.5 volts by T4.

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