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Low Power High Speed Sense Latch

IP.com Disclosure Number: IPCOM000082775D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Chu, JL: AUTHOR [+2]

Abstract

These cross-coupled field-effect transistor (FET) sense latches utilize lower power and provide faster response than conventional differential memory sense amplifiers.

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Low Power High Speed Sense Latch

These cross-coupled field-effect transistor (FET) sense latches utilize lower power and provide faster response than conventional differential memory sense amplifiers.

Fig. 1 is a first embodiment of the cross-coupled sense latch and includes T1 and T2 as bootstrap driver load devices for the cross-coupled pair T3 and T4. T5 is a clocked pulldown device for the latch. T6 and T7 are feedback devices for controlling the gate potential of T1 and T2. T8 and T9 allow precharging of the gates of T1 and T2. Bit lines B/L are connected to charge storage dynamic memory cells, not shown.

The circuit of Fig. 1 operates as follows. During standby, both B/L's and the gates of T1 and T2 are restored to Vref through T8, T9, T11 and T12 by clock pulse phase 1. During access, a memory cell is selected and a small voltage difference develops between nodes A and B. The polarity of the signal depends upon whether the selected storage cell is in a charged or discharged state. Assuming that the voltage at node A is lower than the voltage at node B, when a sufficient voltage difference appears across nodes A and B phase 2 comes up and both T3 and T4 start to turn on. Due to the cross coupling of T3 and T4 node A drops faster than node B, causing T3 to be turned on and T4 off. The cross coupling of the gates of T6 and T7 causes T6 to be on and T7 to be off.

A short time, about 10-20 nanoseconds, after phase 2, phase 3 comes up. Since T6 is on, node D and the gate of T1 are ground...