Browse Prior Art Database

Testing Multichip Substrates

IP.com Disclosure Number: IPCOM000082776D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Bittner, TL: AUTHOR

Abstract

This technique allows preassembly testing of complex metallurgical interconnections on substrates, which are designed to support a plurality of closely spaced integrated circuit chips. High-density wiring and multiple levels of metallurgy on a large multichip ceramic or silicon carrier pose a difficult testing problem. Testing must include all level-to-level shorts, shorts on the same level and continuity of all via holes and lines. his testing must be performed on the chip side of the substrate, since all of the wiring is not accessible to the back of the substrate.

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Testing Multichip Substrates

This technique allows preassembly testing of complex metallurgical interconnections on substrates, which are designed to support a plurality of closely spaced integrated circuit chips. High-density wiring and multiple levels of metallurgy on a large multichip ceramic or silicon carrier pose a difficult testing problem. Testing must include all level-to-level shorts, shorts on the same level and continuity of all via holes and lines. his testing must be performed on the chip side of the substrate, since all of the wiring is not accessible to the back of the substrate.

Testing complexity can be reduced if the number of test probes and number of probings are reduced. One technique useful to accomplish this result is to utilize temporary interconnections between lines normally isolated from each other. This technique is commonly referred to as daisy chaining.

Temporary interconnections between metallurgical lines 10 and 12, to be associated with chip pads 14 and 16 are deposited on substrate 18, as shown in Fig. 1. The lines may be evaporated chromium-copper-gold, for example. An extension 20 is provided which brings lines 10 and 12 into close proximity. Assuming a controlled collapse reflow chip mounting is used, solder pads are deposited at all chip pad locations, including locations 14 and 16. Also included with solder pad deposition is a solder link 22, which effectively connects line 10 to line 12 creating one part of a daisy chain....