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Multiple Selective Write Alterable Read Only Storage

IP.com Disclosure Number: IPCOM000082784D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Wilder, DL: AUTHOR [+2]

Abstract

This teaches that a selected pattern can be sequentially written into a nonvolatile memory array, by the selected application of voltages for selected times.

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Multiple Selective Write Alterable Read Only Storage

This teaches that a selected pattern can be sequentially written into a nonvolatile memory array, by the selected application of voltages for selected times.

Each of the devices in the array will have their gate biased to the half-write level, and a series of sequential incoming addresses are synchronized with suitable data bits to cause the parasitic capacitances on the drains of selected devices to be biased to the half-write level, to cause the selected devices to be written. These parasitic devices, when so charged, maintain the drains of the selected devices at the voltage level for a time sufficient to write the devices, even though the address signal or the data signal has shutdown. In this way, the address signal and/or the data signal need not be powered up for the entire required write time.

Select write is accomplished in the following way. In the figure the gate lines 10, 11, and 12 of the nonvolatile devices 13, 14, and 15 which are to be written are connected in common. The gate lines 20, 21, and 22 of decoded devices 23, 24, and 25 are connected to a suitable decoder 26, while the gate 29 of a data device 30 is coupled to a pulse source 31.

Devices 32, 33, and 34 are connected as diodes to a common node 35 and each of these diodes have their respective drains coupled to the sources of the array 13, 14, and 15. Similarly, the decoder devices are 23, 24, and 25 are connected to the drains of the ac...