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Circuit Redundancy

IP.com Disclosure Number: IPCOM000082785D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Cassidy, BM: AUTHOR [+5]

Abstract

Described is a circuit redundancy scheme for a nonvolatile semiconductor memory array in which the array is formed of blocks, each of which is located in its own isolated epi pocket. To isolate and substitute redundant blocks of memory in such nonvolatile memory arrays, it is necessary to use, as shown in Fig. 1, a pocket control memory 10 which is coupled in parallel to a pocket switch 11 and an array steering circuit 12. These are, in turn, coupled to an isolated memory array 15 which has associated therewith isolated redundant arrays 16 and 17. The steering circuit 12 couples the array 15, 16, and 17 to a final sense amplifier 19.

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Circuit Redundancy

Described is a circuit redundancy scheme for a nonvolatile semiconductor memory array in which the array is formed of blocks, each of which is located in its own isolated epi pocket. To isolate and substitute redundant blocks of memory in such nonvolatile memory arrays, it is necessary to use, as shown in Fig. 1, a pocket control memory 10 which is coupled in parallel to a pocket switch 11 and an array steering circuit 12. These are, in turn, coupled to an isolated memory array 15 which has associated therewith isolated redundant arrays 16 and 17. The steering circuit 12 couples the array 15, 16, and 17 to a final sense amplifier 19.

The pocket control memory 10 is used to select which of the array pockets are to be utilized and DC biased when performing gang erase, gang write, selective write, and reading of the main array. The function of the array steering circuit 12 is to isolate each array during the read and gang write and direct the proper signal to the final sense amplifier

The epi pocket switch 11, shown in greater detail in Fig. 2, is used to provide independent epi voltage controls on each of the arrays in the memory 15 and in the redundant arrays 16 and 17. Due to the nature of defects such as, for example, array epi to gate shorts, it is not beneficial to apply large voltage extremes to defective epi pockets without potentially damaging other support circuits associated with the memory, or disturbing array cells in an adjacent good pocket.

Shown in Fig. 2 in schematic form and represented by a single device is a memory array 20, which is provided with an array gate line 21 and an array epi line 22. For a normal write situation the array gate line 21 is held at +20 volts and the array epi line 22 is held at -15 volts. However, if there is a short between the array gate/line 21 and the array epi, the array epi will rise above the -15 volt level and the array gate line 21 will be pulled down below +20 volts. This situation results in an unsatisfactory write condition.

Alternately, if the array pocket is defective the epi pocket switch 11 for that pocket will not pull down the array epi line down to -15 volts, but instead will let it float. Consequently, the array gate line 21 will not be below +20 volts and it still will be possible to write in the remaining pockets of the array.

In the instance where the epi pocket is defined as being a good pocket, then the voltage VP1 applied to the gate of transistor T6 will be approximately -2 volts and voltages V02, applied to the base of transistor T1, and VQ1, applied to the gate of transistor T7, and VS1 applied to the gate of transistor T8, will all be at - 15 volts. Voltage VOS applied to the gates of transistors T9 and T10 is set to zero volts and voltage VS applied to the collector of transistor T1 is at +20 volts.

During the write condition the array epi input to transistor T9 is also held at -15 volts and the input to transistor T10 is held at zero volts...