Browse Prior Art Database

Sequential Register

IP.com Disclosure Number: IPCOM000082786D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

Described is a shift register-binary counter in which flip-flops connected in a loop provide both the register and the counter function.

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Sequential Register

Described is a shift register-binary counter in which flip-flops connected in a loop provide both the register and the counter function.

The figure depicts a first latch L1 formed of cross-coupled transistors T1 and T2, whose bases and collectors are cross coupled to one another and to current switch transistors T3 and T4. The emitters of the flip-flop transistors T1 and T2 are connected to the collector of one of a pair or transistor T5 in a second current switch. The collector of the other transistor T6 of this second current switch is connected to the emitters of the first current switch (transistors T3 and T4).

An identical latch L2 comprised of flip-flop transistors T7 and T8, first current switch transistors T9 and T10 and second current switch transistors T11 and T12 is coupled in a loop to the first latch L1, as shown in the figure.

When clock input node 20 is positive the first latch L1 is disabled and the second latch L2 is enabled. Nodes 21 and 22 at the collectors of transistors T1 and T2 reflect inputs applied to the base inputs 23 and 24 of current switch transistors T3 and T4. When the clock input node 20 is negative, the data at nodes 21 and 22 is latched into latch L1 and is reflected at the latch output through the current switch, comprised of transistors T9 and T10, coupled to the second latch L2. The second latch L2 simultaneously becomes disabled.

The clock transition must be fast enough to switch the current I1 in the cur...