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Sampled Charge Amplifier

IP.com Disclosure Number: IPCOM000082787D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

A new type of amplification system is described which combines analog and digital techniques.

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Sampled Charge Amplifier

A new type of amplification system is described which combines analog and digital techniques.

The first step is to develop a very small voltage difference on two capacitors C1 and C2. Initially the capacitor voltages are near zero. Then they are allowed to be charged by the collector currents of transistors T1 and T2. If they are allowed to charge to two volts, a difference voltage of 2 MV will be developed if the two collector currents differ by 0.1%. This correlates to an input voltage of 29 microvolts.

The second step is to set a balanced latch with the difference voltage on C1 and C2. The latch is formed by transistor T3 and T4. The latch will begin to determine its final state when the capacitor voltage is sufficient to turn T3 or T4. The state of the latch is then transferred to a flip-flop (FF) 10, which latches its input voltage on a negative transition and holds it until the next negative transition of its control input. The FF output is then used to develop an output voltage whose range is I(2)RL. It is then converted back to an analog voltage by passing it through a low-pass filter 12. In its simplest and most practical form the filter is merely a shunt capacitor 14.

The system works as follows: at time t0 node 16 goes negative and discharges C1 and C2. Transistors T3 and T4 are off and their emitter base junctions are reversed biased. At time t1, the sample pulse goes positive and C1 and C2 charge positive, developing a difference voltage based on th...