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Carriage Control with Variable Line Spacing

IP.com Disclosure Number: IPCOM000082795D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 95K

Publishing Venue

IBM

Related People

Halich, VV: AUTHOR [+2]

Abstract

A carriage control can be modified to permit dynamic mixing of 6 and 8 lines per inch (LPI) spacing on the same form, by making the following modifications to the Forms Control Buffer (FCB): (1) the first byte the FCB Load Data is redefined to allow for mixed mode operation, (2) coding definition for 6/8 LPI is changed to allow for 6/8 LPI specification on all FCB addressed lines, and (3) the last address of the FCB is redefined. Additional logic is added to allow the carriage operation to perform the mixed mode spacing/skipping, as specified in the FCB and the carriage command. Presently the FCB data byte coming from a CPU is defined as follows: Bits 0 1 2 3 4 5 6 7 P Definition Not Used F 8 4 2 1 P Loaded into FCB.

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Carriage Control with Variable Line Spacing

A carriage control can be modified to permit dynamic mixing of 6 and 8 lines per inch (LPI) spacing on the same form, by making the following modifications to the Forms Control Buffer (FCB):
(1) the first byte the FCB Load Data is redefined to allow for mixed mode operation, (2) coding definition for 6/8 LPI is changed to allow for 6/8 LPI specification on all FCB addressed lines, and (3) the last address of the FCB is redefined. Additional logic is added to allow the carriage operation to perform the mixed mode spacing/skipping, as specified in the FCB and the carriage command. Presently the FCB data byte coming from a CPU is defined as follows: Bits 0 1 2 3 4 5 6 7 P

Definition Not Used F 8 4 2 1 P

Loaded into FCB.

Thus, bits 0, 1, 2 are not used; hence these are not loaded into the FCB. Bit 3 is designated as a flag (F) bit with dual purpose. When the F-bit is in Address One of the FCB, it signifies that forms spacing is to be performed at 8 LPI; otherwise, absence of the F-bit in Address One signifies that forms spacing is to be performed at 6 LPI. The F-bit in any address other than Address One, signifies the end of the FCB form and this results in a wraparound from that address to Address One on the next movement of carriage spacing. Bits 4, 5, 6, 7 are channel bits with their normal binary values. Presently only binary values of channels 1 through 12 are acceptable.

A pictorial layout of an FCB image is shown in Fig. 1. An FCB Load Command, issued from the CPU, would load such an image of the required form into the FCB located in the printer. Thus, in Fig. 2, blocks 1, 2, 3, and 4 are used to load an FCB image from CPU into the printer. Once the FCB is loaded, the FCB Address Triggers 4 keep the FCB in sync with the forms movement by the carriage. AB: At the end of FCB Load Command, the FCB Address Triggers 4 are set to Address One and the buffer data from Address One is read out and stored in FCB Data register 5. The FCB Address One Latch 6, in Fig. 3, is set in this case, and the fact that a flag bit is stored in the FCB Data register 5 (Fig. 2) consequently causes AND gate 7 (Fig. 3) to set the 8/6 LPI latch 28. Thus, all subsequent spacing will be performed at 8 LPI, until a new FCB Load Command loads an FCB image that does not contain a flag bit in Address One.

The definition of the FCB Data byte for mixed mode operation is as follows:

Channel 15

End of Form

1 1 1 1

Bits 0 1 2 3 4 5 6 7 P

Definitions Not Used MM 8 LPI 8 4 2 1 P

Loaded in- Loaded into FCB

to a latch.

Unused bit 2 will have a new meaning of Mixed Mode bit (MM-bit), if bit 2 is present in the first byte of the FCB Data transferred during FCB Load Command.

1

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The MM-bit will be loaded into a latch called the Mixed Mode latch 38 (MM latch). The presence of the MM latch modifies the meaning of the remaining bits 3, 4, 5, 6, 7. In mixed mode operation, bit 3 specifies 8 LPI; the absence of bit 3 specifies...