Browse Prior Art Database

2N Phase Generator

IP.com Disclosure Number: IPCOM000082810D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR

Abstract

There is a great need for phase generators to provide clocking signals for field-effect transistor (FET) circuits operating in dynamic logic.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 73% of the total text.

Page 1 of 2

2N Phase Generator

There is a great need for phase generators to provide clocking signals for field-effect transistor (FET) circuits operating in dynamic logic.

This is a method for designing phase generators based on the use of Set- Reset (S-R) flip-flops. Such a S-R flip-flop is a box with two inputs (Set and Reset) and two complementary outputs Q and Q. If Set is equal to 1, Q will be forced to 1, if Reset is equal to 1, Q will be forced to 0; if Set = Reset = 0, Q will not change. In some technologies one input Set or Reset is dominant. It is possible to design a 2N-phase generator by using N Set-Reset flip-flops connected in binary loops. The Set and Reset input signals will be used as generator output signals.

In order to obtain cyclic operation, any N-bits arrangement of the generator outputs should be changed from its state (No) to the next state (N1) by changing one and only one bit.

For instance, suppose that a nonoverlapped (Fig. 1(b)) 4-phase generator (N=2) is to be built, 2 S-R flip-flops SR1 and SR2 are required (see Fig. 1(a)). In operation outputs Q1 and Q2 should provide the following sequence: Q2 Q1 Steps

0 0 1

0 1 2

1 1 3

1 0 4

0 0 1

The rule should be:

Set Q1 to go from step 1 to step 2.

Set Q2 to go from step 2 to step 3.

Reset Q1 to go from step 3 to step 4. Reset Q2 to go from step 4 back to step 1.

This set and reset information will be obtained by logically combining output signal Q1, Q2, Q1 and Q2. Set Q1 = Q1 . Q2 Set Q2 = Q1 . Q2 Rese...