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A Method for Analyzing Clock Tree Design in a Digital Circuit Through Cross-Domain Interaction

IP.com Disclosure Number: IPCOM000082819D
Original Publication Date: 2005-Feb-28
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Abstract

Disclosed is a method for generating reports based on static timing analysis for the purposes of analyzing and improving the clock tree structures contained in a digital design. The primary focus of this method is on the relationship between clock domains.

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A Method for Analyzing Clock Tree Design in a Digital Circuit Through Cross -Domain Interaction

    One of the major milestones of digital circuit implementation is the insertion of clock trees. Static Timing Analysis (STA) is used during the physical design to drive the timing-driven placement tools as well as to validate the insertion, optimization, and operation of these clock trees. Static timing analysis tools such as IBM EinsTimer* use various timing reports such as clock skew reports, setup/hold checks, slack histograms, and endpoint reports to aid in the analysis of timing violations in the design. When clock trees are first inserted into the design, problems with the structure or latency of the clock trees can lead to a huge number of timing violations. This explosion of violations makes if difficult to use the standard setup and hold checking reports to analyze the problems introduced by the clock trees. This is particularly true for designs that contain a large number of clock trees that interact with one another or a design where the clock structure or interaction is not well understood.

    The traditional approach for solving this clock intersection problem is to generate a clock skew report after clock insertion and attempt to minimize the skew on all clock trees. Once the overall skew has been optimized the physical designer then attempts to force the average arrival times at the leaves of each clock tree to roughly match the ideal clock timing targets. This is called clock alignment and is often the cause of the greatest number of violations in the timing reports. The primary drawback of this approach is that it is very time consuming, difficult to analyze, iterative, and assumes that the clock alignment can be matched to the ideal timing targets. It also does not take into consideration that the physical clock tree may require clock basins (i.e. early or late subtrees) that were not properly specified or understood by the logic design team.

    This invention consists of a class of reports generated by a STA tool such as IBM EinsTimer to aid in the analysis of complex clock designs and their interaction. While standard timing reports in STA tools tend to be based on individual clock or data phase tags, this invention describes a method of reporting timing violations based on clock and data phase combinations. The clock/data phase combinations and their slacks directly reflect the structure and interaction of the of the clock trees implemented in the design. These reports can improve the design cycle time of processing a complex digital circuit by specifically identifying inter-clock domain and intra-clock domain violations. This invention can implemented directly in the report generation code of the STA tool or as a post-processing step using standard timing reports as input. Both approaches have has been implemented as prototypes. The implementations are based on phase tags using the standard analysis approach defined in mo...