Browse Prior Art Database

Read Only Store Memory Extension

IP.com Disclosure Number: IPCOM000082845D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Kane, MH: AUTHOR [+2]

Abstract

When it is necessary to add additional read-only store (ROS) chips to a limited system and it is necessary to address more than one chip of ROS, then additional logic must be used to direct the address to the proper ROS memory area. This logic makes use of two chip select lines, (CSEL1 and CSEL2), and a memory select line which can be conditioned by the host logic. The three clock terms C1, C2, and C3 which are used to do the basic logic clocking are also used in the chip select logic.

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Read Only Store Memory Extension

When it is necessary to add additional read-only store (ROS) chips to a limited system and it is necessary to address more than one chip of ROS, then additional logic must be used to direct the address to the proper ROS memory area. This logic makes use of two chip select lines, (CSEL1 and CSEL2), and a memory select line which can be conditioned by the host logic. The three clock terms C1, C2, and C3 which are used to do the basic logic clocking are also used in the chip select logic.

The logic would condition the Memory Select (MEMSEL) line and then establish the address it wished to access in the new memory area. It takes two cycles of the logic (Fig. 2) to establish this address. During this time the chip select logic is being set up so that the new address will be directed to the proper memory area. Time A (Fig. 2) is the time that MEMSEL is conditioned, but the signal from the host logic is not gated on until the first T2 in B time.

The chip select logic consists of two control latches, four gates for CS 1-4 (Fig. 1) and three decodes from the clock terms named Q1, T1 and T2). This logic is shown in detail (Fig. 3).

The relationship of the three clock pulses C1, C2, C3 is shown in Fig. 3.

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