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Browse Prior Art Database

Frequency Doubler

IP.com Disclosure Number: IPCOM000082853D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Hong, JH: AUTHOR

Abstract

A frequency doubling circuit is provided for use in a digital repeater having self-compensating clock placement to double the frequency of the input biphase encoded data, before it is applied to an acoustic surface-wave filter. This circuit, including the acoustic surface-wave filter, is suitable for LSI (large-scale integration) implementation.

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Frequency Doubler

A frequency doubling circuit is provided for use in a digital repeater having self-compensating clock placement to double the frequency of the input biphase encoded data, before it is applied to an acoustic surface-wave filter. This circuit, including the acoustic surface-wave filter, is suitable for LSI (large-scale integration) implementation.

The biphase encoded data is applied to the current switch emitter-follower T1, T2, T3 and T4. The in phase and out-of-phase outputs are tied together by dotting at the outputs of T3 and T4. This output produces a sharp negative going spike at each transition of the input data, as shown at the base input of T5 in Fig.
1.

The second current switch emitter-follower T5, T6, T7 and T8 amplifies these spikes and drives the filter. The reference voltage VH applied to T6 is set at the base line of the spikes, in order to obtain maximum gain.

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