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Intermittent Signal Fault Generator

IP.com Disclosure Number: IPCOM000082862D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wilson, CW: AUTHOR

Abstract

The intermittent signal fault generator described is useful as an evaluation tool for diagnostic programs, error recovery procedures and serviceability packages for systems or unit equipment. It is designed to eliminate, on a repetitive basis, one pulse from a serial stream of pulses on a digital logic signal line. The drawing does not show the line or how the pulse is eliminated and is limited to the generation of a signal which may typically be dot ORed with the signal line at any appropriate place.

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Intermittent Signal Fault Generator

The intermittent signal fault generator described is useful as an evaluation tool for diagnostic programs, error recovery procedures and serviceability packages for systems or unit equipment. It is designed to eliminate, on a repetitive basis, one pulse from a serial stream of pulses on a digital logic signal line. The drawing does not show the line or how the pulse is eliminated and is limited to the generation of a signal which may typically be dot ORed with the signal line at any appropriate place.

The frequency of the fault is set by a rotary switch 10 connected to a counter 11 and adapted to establish an appropriate logic level at one input of an AND gate 12 when the counter 11 reaches the value set into switch 10. The lowest order of counter 11 is connected to the second input of gate 12 only. Thus, gate 12 will provide an appropriate output one clock time following the value set into switch 10. An external clock from the device under test is applied to counter 11 and causes it to count. Alternatively, an oscillator 14 may be substituted for the external clock signals which drive counter 11.

When the preselected count is decoded, as described above, a signal is transmitted via inverters 15 and 16 for eliminating a logical pulse. Trigger circuit 17 is preset at this time and a counter reset signal generated at the next pulse via AND gate 18 and OR gate 19. Trigger 17 is reset for the next sequence by the following external...