Browse Prior Art Database

Interleaved Cycle Steal Burst Circuitry

IP.com Disclosure Number: IPCOM000082865D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Miller, TH: AUTHOR [+2]

Abstract

This interleaved cycle steal burst circuitry ensures transfer of a minimum size block of data by one I/O device operating in a cycle steal burst ode, prior to being interrupted by a higher priority cycle steal I/O device. When an I/O device operates in a cycle steal burst mode, the channel is dedicated to that device and may cause overrun in other devices attached to the channel. Hence, it is necessary to ensure that mode, prior to being interrupted by a higher priority cycle steal I/O device. When an I/O device operates in a cycle steal burst mode, the channel is dedicated to that device and may cause overrun in other devices attached to the channel. Hence, it is necessary to ensure that the other devices on the channel do not overrun.

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Interleaved Cycle Steal Burst Circuitry

This interleaved cycle steal burst circuitry ensures transfer of a minimum size block of data by one I/O device operating in a cycle steal burst ode, prior to being interrupted by a higher priority cycle steal I/O device. When an I/O device operates in a cycle steal burst mode, the channel is dedicated to that device and may cause overrun in other devices attached to the channel. Hence, it is necessary to ensure that mode, prior to being interrupted by a higher priority cycle steal I/O device. When an I/O device operates in a cycle steal burst mode, the channel is dedicated to that device and may cause overrun in other devices attached to the channel. Hence, it is necessary to ensure that the other devices on the channel do not overrun.

If a fixed length of time is allocated to initiate and to terminate a cycle steal operation irrespective of the number of bytes transferred, the data rate is low when a short burst is used to prevent overrun. The data rate is improved by permitting a pause in the cycle steal burst mode for an I/O device transferring a large block of data and enabling an I/O device transferring a small block of data to operate, and thereafter upon completion of the transfer of the small block of data, the transfer of the larger block of data resumes.

Adapters 30, 40, and 70 attach to CPU 20 which in turn connects with storage 10 to form a computer system, together with I/O devices 31, 41 and 71. Adapters 30, 40 and 70 have the highest, next highest and lowest cycle steal priorities, respectively. Adapter 40 in this particular instance contains the interleave cycle steal burst circuitry shown in Fig. 2. Adapter 30 transfers small blocks of data but needs a fast response time, whereas adapter 40 transfers large blocks of data.

Cycle steal requests are initiated by an adapter by raising its cycle steal request line. The cycle steal request line 72 in adapter 70 is logically combined by OR circuit 73 with a cycle steal request on line 74 from a lower priority adapter, not shown. The cycle steal request signal from OR circuit 73 is passed to OR circuit 43 of adapter 40, which logically combines it with the cycle steal request signal on line 42. The cycle steal request signal from OR circuit 43 is then logically combined by OR circuit 33 with the cycle steal request signal on line 32, and the resulting cycle steal request signal is passed to CPU 20.

CPU 20 is responsive to the cycle steal request signal and generates a grant signal on line 21 and an I/O cycle signal on line 22. The cycle steal grant signal on line 21 is chained back through each adapter via AND circuits 34, 44 and 75. The first adapter receiving the grant signal assumes control if it has requested a cycle steal, because it will then inhibit the transfer of the grant signal to a lower priority adapter. After an adapter receives the cycle steal grant signal, it responds with a valid signal to CPU 20 on line 23.

If the...