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Phase Discriminator for a Phase Locked Oscillator

IP.com Disclosure Number: IPCOM000082873D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Prentky, PI: AUTHOR

Abstract

A phase discriminator generates true phase errors, early and late, by comparing input data and clock signals. For late phase errors, a delay is used to center the data within a window.

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Phase Discriminator for a Phase Locked Oscillator

A phase discriminator generates true phase errors, early and late, by comparing input data and clock signals. For late phase errors, a delay is used to center the data within a window.

The phase discriminator incorporates a special set-reset flip-flop, which is defined by the following truth tables: Reset Dominates Set Dominates

S R Q (t+1) S R Q (t+1)

0 0 Q (t) 0 0 Q (t)

0 1 0 0 1 0

1 0 1 1 0 1

1 1 0 1 1 1.

Early phase error is measured by the logic diagram shown in NOR gate implementation in Fig. 1. This logic generates the early phase error for any data pulse duration < 1/2T, where T is the clock pulse duration. The + set input to the -AND ensures that the output will be inhibited in the case of a large, late phase error, when set and reset can partially overlap.

The late phase error is derived by using NOR logic gates, as indicated in Fig.
2. A block diagram representing the schematic circuit of Fig. 2 is presented in Fig. 3.

The delay is used for positioning the desired data within the Q2 window. In the case of late phase error, the magnitude of delay does not affect the generated phase error. FF2 gates out all but the desired information.

By this network, the phase discriminator eliminates the need for a single-shot, which is conventionally used, but which requires timing adjustment.

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