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Delta Order Hold Sample and Hold Function

IP.com Disclosure Number: IPCOM000082877D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Granata, PJ: AUTHOR

Abstract

A delta order sample and hold network compensates for phase lag in a zero order hold network, by adding a delta error voltage to the original staircase function. The error voltage is developed in response to the amplitudes of adjacent staircase steps.

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Delta Order Hold Sample and Hold Function

A delta order sample and hold network compensates for phase lag in a zero order hold network, by adding a delta error voltage to the original staircase function. The error voltage is developed in response to the amplitudes of adjacent staircase steps.

In operation, an input signal is passed through a sample and hold circuit 10, and the output A of this circuit is fed to a differentiator 12. The differentiated output is a series of pulses that occur at sampling time, and which vary in amplitude and changes polarity as the input signal passes through a peak.

The differentiated signal B is then applied to a sample and hold circuit 14, and its output C is the staircase error signal, which is proportional to delta height differences in the original staircase function from the sample and hold circuit 10.

In order to control the phase correction over a zero order hold network, a variable-gain amplifier 16 is provided at the output of the sample and hold circuit 14 and at the input of a summer 18. The gain amplifier varies the amount of delta error voltage that is to be added to the original staircase function.

When the delta error staircase function is added to the original staircase function, the result is a staircase function that may be set in phase with the input signal, or phase lead the input at certain frequencies, depending on the particular gain setting. Thus, it is possible to have a sample and hold function that provi...