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Three Phase Josephson Tunneling Device Shift Register

IP.com Disclosure Number: IPCOM000082903D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+3]

Abstract

Fig. 1 shows a shift register design using three Josephson tunneling devices per bit and symmetrical square waves as input clocks. The approach used eliminates the requirement for the use of nonsymmetrical waveforms, as shown in the IBM Technical Disclosure Bulletin, Vol.l6, No.9, Feb. 1974, pp.3040 and 3041 in an article entitled "Josephson Tunneling Device Shift Register" by Y. L. Yao, and further eliminates the critical timing of clocks in the circuit shown in the IBM Technical Disclosure Bulletin, Vol.16, No.5, Oct. 1973, pp.1466 and 1467 in an article entitled "Pseudo Single-Phase Josephson Tunneling Device Shift Register" by Y. L. Yao.

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Three Phase Josephson Tunneling Device Shift Register

Fig. 1 shows a shift register design using three Josephson tunneling devices per bit and symmetrical square waves as input clocks. The approach used eliminates the requirement for the use of nonsymmetrical waveforms, as shown in the IBM Technical Disclosure Bulletin, Vol.l6, No.9, Feb. 1974, pp.3040 and 3041 in an article entitled "Josephson Tunneling Device Shift Register" by Y. L. Yao, and further eliminates the critical timing of clocks in the circuit shown in the IBM Technical Disclosure Bulletin, Vol.16, No.5, Oct. 1973, pp.1466 and 1467 in an article entitled "Pseudo Single-Phase Josephson Tunneling Device Shift Register" by Y. L. Yao.

Fig. 1 shows a plurality of shift register stages 1-3, including Josephson junction devices, Q1-Q3, respectively, to which phased gate currents, Phi 1-Phi 3, respectively, are applied. Each of the Josephson tunneling devices is terminated by a resistance RO through which current is diverted when its associated Josephson device switches, and which acts as a control line for a succeeding Josephson device.

A common DC bias control, shown by the dashed line in Fig. 1, can be utilized to operate Josephson devices Q1-Q3 (which are identical) in the antiparallel mode of operation, as shown in Fig. 3.

This bias supply is not needed when the devices are operated in the parallel mode. Data s applied to the circuit via a control line of device Q1 labelled DATA IN.

Fig. 2 shows three...