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Masking for One Device Cell Memories Using Self Registering Metal To Polysilicon Contacts

IP.com Disclosure Number: IPCOM000082909D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

Kalter and Miller (Ref. 1) have described a masking scheme for one-device cell memories that uses a single layer of polysilicon, and which provides a self-registering metal-to-polysilicon gate contact. With their masking scheme, nitride over the storage plate must be completely removed before thermal oxidation, and the oxide over the gate must be removed to reveal the gate for contacting, thus requiring extra thick thermal oxide.

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Masking for One Device Cell Memories Using Self Registering Metal To Polysilicon Contacts

Kalter and Miller (Ref. 1) have described a masking scheme for one-device cell memories that uses a single layer of polysilicon, and which provides a self- registering metal-to-polysilicon gate contact. With their masking scheme, nitride over the storage plate must be completely removed before thermal oxidation, and the oxide over the gate must be removed to reveal the gate for contacting, thus requiring extra thick thermal oxide.

Two alternate masking schemes are described here which eliminate these potential processing problems. The new masking schemes also employ a single level of polysilicon and use the same number of basic masking steps (five) as the Kalter and Miller approach. Description.

The simplest possible ROX (recessed oxide) process for one-device cell memories involves four masking steps: ROX definition; polysilicon gate and polysilicon storage plate definition; contact hole-to-polysilicon gate, polysilicon plate and diffused regions; and metallization definition as shown at A in the figure. This process has been used to fabricate experimental one-device cell memory arrays (Ref. 2). An extension of this process, called ROX/MOD (ROX modified) has been described by Kalter and Miller (Ref. 1).

The ROX/MOD approach uses a fifth mask which allows a self-registering metal-to-polysilicon gate contact, thus yielding a smaller cell and improved contact reliability. The five ROX/MOD masking steps as shown at B in the figure are: ROX definition, polysilicon gate and plate definition, shield over the polysilicon gate, contact hole-to-polysilicon plate and to diffusion, and metallization. The ROX/MOD approach uses five masks and a single layer of polysilicon, from which both gate and plate are defined in a single masking step. Consequently this approach will henceforth be referred to as the GATE+PLATE process.

The addition of the fifth masking step to form the GATE+PLATE process, affords an additional degree of processing and masking flexibility that has not been recognized thus far. Described are two alternate masking schemes which offer certain processing advantages, in exchange for having the plate and gate misaligned relative to one another. The new masking scheme shown at C in the figure consists of: ROX definition, polysilicon gate definition, polysilicon plate definition, contact hole to-polysilicon plate and diffusion, and metallization. Masking steps two and three can be interchanged, resulting in the steps shown at D in the figure.

Masks two and three of the new GATE/PLATE (C) and the new PLATE/GATE (D) processes are different from masks two and three of the previous GATE+PLATE process (B). The essential difference between the new schemes and the Kalter and Miller approach, is that now the gate and plate areas are defined sequentially in two separate masking steps. Thus the gate and plate regions are no longer aligned precisely rel...