Browse Prior Art Database

Interface Between Terminal and Repeater

IP.com Disclosure Number: IPCOM000082913D
Original Publication Date: 1975-Feb-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Widmer, AX: AUTHOR

Abstract

The interface in Fig. 1 attaches a terminal 17 to a loop repeater element 9 in a loop operating in the synchronous mode, as for example with frames. The distance between these two separate boxes is such that transmission line techniques are used for communication, but it does not extend far enough for significant attenuation and distortion. To allow for easy movement and rearrangement of terminals, hot pluggability is required and enables terminal 17 to be attached to or detached from a repeater port without disturbing the signals on the operating loop 10.

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Interface Between Terminal and Repeater

The interface in Fig. 1 attaches a terminal 17 to a loop repeater element 9 in a loop operating in the synchronous mode, as for example with frames. The distance between these two separate boxes is such that transmission line techniques are used for communication, but it does not extend far enough for significant attenuation and distortion. To allow for easy movement and rearrangement of terminals, hot pluggability is required and enables terminal 17 to be attached to or detached from a repeater port without disturbing the signals on the operating loop 10.

The interface must provide DC isolation between loop and terminal elements to permit clean technical solutions for separate loop and terminal ground and power. The number of interface lines is minimized for cost and reliability reasons. A single-loop repeater element 9 can be equipped with several ports or terminal interfaces. The port circuitry drains a minimum power from loop 10.

Repeater 9 consists of a receiver 7 which samples the signal from the loop 10 to extract a clock and a retimed biphase code signal, Widmer U.S. patent 3,805,180. The recovered 2fo clock then shifts the retimed code half-bit by half- bit through a register of any length into a driver 8, which forms a signal suitable for further transmission along loop 10. Two successive shift cells FF1, FF2 with the attached port circuitry are shown in Fig. 1. In flip-flops FF1 and FF2, the data input level D is transferred to the Q output at the instant when the clock input rises. These are edge-triggered flip-flops.

In operation, a biphase signal is continuously sent from FF1 through a line driver 12, transformer 13, outbound transmission line 14 and interface plug 15 to a receiver 16 located in the terminal 17.

Receiver 16 can be the same as the one in the repeater input. It extracts from the outbound signal 1 a 2fo clock equal to the half-bit rate for use in terminal 17. If terminal 17 is not in the transmitting mode, its driver 18 facing the ternary port receiver input 19 is inhibited, resulting in near zero differential voltage at input 19. For this condition, both outputs 3 and 4 of the ternary receiver 20 are at the up level and the coded signals from FFl pass unchanged at the clock rate to FF2 and driver 8.

When terminal 17 wants to enter its own coded signal on loop 10, its driver sends a signal 2 over the inbound transmission line 21, plug 15 and transformer 22 to receiver 20. If the differential voltage at receiver 20 exceeds a specified threshold voltage, output 3 or 4, but not both, will be down depending in the polarity of the signal.

If output 3 is up and 4 down, FF2 (Q) assumes the uplevel at the next clock cycle regardless of the FF1 output. If 3 is down and 4 is up, FF2 (Q) goes to the downlevel. To save loop power, the outbound signal amplitude 1 is made as small as possible and signal 2 on the inbound line as large as practical. The function of the receiver 2...