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High Speed Low Power Inverter

IP.com Disclosure Number: IPCOM000082928D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Arzubi, LM: AUTHOR

Abstract

A restore pulse CS is produced preferably on a semiconductor chip from a chip select pulse CS, by these inverter circuits which dissipates low power, use a small chip area and rapidly drive large loads.

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High Speed Low Power Inverter

A restore pulse CS is produced preferably on a semiconductor chip from a chip select pulse CS, by these inverter circuits which dissipates low power, use a small chip area and rapidly drive large loads.

In the circuit of Fig. 1, when pulse CS is down, capacitor C1 becomes charged through transistor 4 to a voltage +V-V(T). Then when CS is up at a voltage +V, transistor 4 is turned off and the voltage at node A rises to a voltage 2V-V(T), turning on transistor 3 which charges capacitor C1 to the voltage +V, with node C being at ground. After pulse CS goes down, transistor 2 is turned off and node C is driven up by transistor 1 which now has at its gate the voltage at node C +V, rapidly producing the restore pulse CS with a magnitude of +V.

The circuit of Fig. 2 is similar to that of Fig. 1, except that transistors 5 and 6 are added with node B being connected additionally to the gate of transistor 5, the gate of transistor 6 being connected to the gate of transistor 2, and the restore pulse or not chip select pulse CS being derived from node D.

In the operation of the inverter circuit of Fig. 2, when pulse CS is down, capacitor C2 becomes charged to a voltage +V-V(T) and then when pulse CS goes up, the voltage on node A goes to 2V-V(T). Consequently. node B is charged to +V. After pulse CS returns to its down state, transistor 2 is turned off and node C rises quickly to +V with node B's voltage increasing to 2V, which causes transistor...