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Dynamic Redundancy and Repair System for Large Mass Storage Unit

IP.com Disclosure Number: IPCOM000082933D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Abrahamsen, R: AUTHOR

Abstract

This mass semiconductor storage system utilizes a plurality of multiple array semiconductor wafers which may be electronically personalized to use partially defective memory arrays, both during manufacture and assembly and later during use in the field.

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Dynamic Redundancy and Repair System for Large Mass Storage Unit

This mass semiconductor storage system utilizes a plurality of multiple array semiconductor wafers which may be electronically personalized to use partially defective memory arrays, both during manufacture and assembly and later during use in the field.

A plurality of full, undiced, semiconductor wafers each including a number of independent random-access memory arrays, or islands, form a Basic Storage Unit. During manufacture each wafer is tested to determine the amount of usable storage within each island. This data is recorded and a plurality of wafers containing a total usable storage area at least as large as the desired memory capacity are assembled.

Physical locations within the total memory address space are allocated and a record is made of the defects within the physical space, corresponding to each logical block of data. Defect information is compiled into a table or Defect Directory and stored in a suitable medium. Thereafter when a block of data is accessed in the memory, only usable physical storage space is accessed.

Fig. 1 shows a typical island organization comprising an array of 256 words by 8 sectors. Each sector contains an 8-byte logical word of 72 bits. Words are accessed by the coincidence of a word address provided by a 1 of 256 decoder, not shown, and a sector address provided by a 1 of 8 decoder. An all-good island is capable of storing 2048 words.

Various types of defects can effect the storage capacity of a particular island. For example, a defect in the decoding or support circuitry can disable all 2048 words. Assuming that no error correction is provided in the system, a defective bit line in a sector will cause a loss of 256 words of storage, one logical word out of each physical word accessed. A defective word line will cause a loss of 8 consecutive logical words, one for each sector. A defective memory cell will cause the loss of only a single word.

Fig. 2 represents a section of physical address space in the memory. The width of the figure represents one word length and the height of the clear areas represent the number of words in a logical block of data to be accessed. The shaded areas represent defective portions of the physical address space.

A logical block of data may contain any number of words and has a starting address A. D represents the number of consecutive words ava...