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APL Compress Array

IP.com Disclosure Number: IPCOM000082935D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dorocak, JP: AUTHOR

Abstract

Array 10, Fig. 1, performs an APL compress function, i.e., it selects a field of INPUT bits and performs a right-justify operation.

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APL Compress Array

Array 10, Fig. 1, performs an APL compress function, i.e., it selects a field of INPUT bits and performs a right-justify operation.

The elements 1 of array 10 are identical and each includes a pair of multiplexers 2, 3, cf. Fig. 2, configured as a cross-point switch. More specifically, if C=0, then inputs at S and W are gated to E and N, respectively. Conversely, if C=1, then inputs at S and W are gated to N and E, respectively.

Array 10 is selected to have M/2/ elements 1, where M is the maximum number of bits to be compressed. Thus, for a four-bit example, sixteen elements are provided in array 10 of Fig. 1. The elements 1 are interconnected, as shown, so as to effect a right justification or packing of the INPUT bits I0, I1, I2, I3 in the appropriate OUTPUT bits 00, 01, 01, 03. Only those bits of INPUT will be present in OUTPUT where the particular one or ones of the CONTROL bits are equal to a binary 1. Any higher order bits of the OUTPUT are forced to 0, as shown by the three examples in Fig. 3.

Array 10 is readily implemented as a large-scale integrated module. It is particularly useful for the instruction decode cycle of a microcoded machine. It makes possible a branch on widely separated bits in the emulated instruction set at efficient speeds and with rather simple circuit hardware.

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