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Array Logic With Random Access Memory

IP.com Disclosure Number: IPCOM000082948D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR

Abstract

Many design problems are encountered by random logic large-scale integration (LSI). Among these are (1) the difficulty in coping with engineering change requirements, (2) the difficulty of interconnecting large numbers of logic circuits in an LSI which allows only a few layers of metallurgy, (3) the severe limitation on the number of logic circuits in a random logic LSI due to the input/output pad requirements, (4) the increased LSI costs where many different part numbers (metallurgy interconnection patterns) are required, and (5) the part number-test pattern proliferation problem.

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Array Logic With Random Access Memory

Many design problems are encountered by random logic large-scale integration (LSI). Among these are (1) the difficulty in coping with engineering change requirements, (2) the difficulty of interconnecting large numbers of logic circuits in an LSI which allows only a few layers of metallurgy, (3) the severe limitation on the number of logic circuits in a random logic LSI due to the input/output pad requirements, (4) the increased LSI costs where many different part numbers (metallurgy interconnection patterns) are required, and (5) the part number-test pattern proliferation problem.

Array logic or structured logic employing read-only memory (ROM) arrays to perform logic, such as the programmable logic array (PLA) technique, is known to solve some but not all of the above mentioned problems, for instance, part numbers and engineering changes. Array logic employing the conventional read- write or random-access memory RAM approach, however, can address all of the above problems, as herein described. Part number requirements are eliminated since all random-access memory chips are exactly the same, and engineering changes can be achieved by storing different bit patterns into the random-access memory through some auxiliary storage (such as a floppy disk). The only obvious disadvantage of this approach is that the random-access memories are volatile and required bit patterns should be loaded with each machine start.

In Fig. 1. the conventional random-access memory organization of m word by one bit is used to demonstrate the proposed approach. Other organizations with more than one bit output per chip may also be employed. The n inputs which, in conventional random-access memory operation, represent the memory address, are now the logic inputs and control bits. The k outputs represent the result of the logic operation. To accommodate sequential logic requirements, a number of outputs are fed back to the inputs. The feedback l...