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Array Logic Structure Using FAMOS Devices

IP.com Disclosure Number: IPCOM000082965D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

DasGupta, S: AUTHOR

Abstract

One way to reduce the silicon area used by writable array logic structures is to use the inherent properties of floating-gate avalanche-injection metal-oxide semiconductors (FAMOS), which have an extra floating gate situated between the normal gate of a field-effect transistor (FET) and the silicon. The normal gate can be electrically controlled to store or erase a charge in the floating gate, which turns the channel on or off.

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Array Logic Structure Using FAMOS Devices

One way to reduce the silicon area used by writable array logic structures is to use the inherent properties of floating-gate avalanche-injection metal-oxide semiconductors (FAMOS), which have an extra floating gate situated between the normal gate of a field-effect transistor (FET) and the silicon. The normal gate can be electrically controlled to store or erase a charge in the floating gate, which turns the channel on or off.

Fig. 1 shows a 2 x 2 search array in which each cell uses two FAMOS devices to provide four states: 00 = "X" (don't care), 01 = "1", 10 = "0", and 11 = "Y" (illegal). Assume that a 1 in a device indicates that it can conduct current. The "write" operation is performed in two steps. Since each cell in the search array has two storage devices, a complete write operation in any row requires writing into the left half of each cell followed by writing into the right halves. Any row in the "read" array is written into during writing into the left halves of cells in the same row of the search array.

To write into row 1, line DL1 in Fig. 1 is raised (assuming N-channel devices throughout) and data to be stored in the left-half devices of each cell is presented on the common LEFT DATA SEARCH/WRITE lines. At the same time, with line DL1 raised, data is stored in the first row of the read array (Fig. 2) by presenting the proper levels to the common write lines. The right halves of the cells in row 1 of Fig. 1 are similarly written into, by raising line DR1 and presenting the proper data to the RIGHT DATA SEARCH/WRITE lines. Thus, by selecting one row at a time. the whole array can be written into. Note that during any write operation, t...