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Photoelectric Sensing of the States of Internal Nodes in Integrated Circuits

IP.com Disclosure Number: IPCOM000082966D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+2]

Abstract

In this method, the use of photodiodes at pertinent nodes and an appropriate light source, the condition (high/low) of these nodes can be determined.

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Photoelectric Sensing of the States of Internal Nodes in Integrated Circuits

In this method, the use of photodiodes at pertinent nodes and an appropriate light source, the condition (high/low) of these nodes can be determined.

In high-density logic circuit chips the task of fault location is almost impossible, since logic networks are complex and the number of primary outputs from the networks are few.

In this method, photodiodes are placed at desired nodes within the circuits, using existing junctions, such as a collector substrate or drain-substrate junctions, as shown in the drawing. At nodes 1, 2, 3 and 4 are placed photodiodes 5, 6, 7 and 8, respectively, which make possible the determining of the condition of the nodes. For example, if node 1 is high, the photodiode 5 connected between node 1 and ground or substrate is reverse biased, and the current flowing is of leakage magnitude (typically less than 100 pA depending on the node characteristics), and is called the dark current.

If the diode 5 is irradiated with a suitable light source, for example a laser, a current starts flowing to ground or substrate discharging node 1. This current can be measured with standard instrumentation. If node 1 happens to be low, the current would be close to zero. The concept illustrates the approach to determining the condition of "buried nets"in a logic network.

Potentially, all the critical nets could be connected to photodiodes which would be placed strategically so as...