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Browse Prior Art Database

Subnanosecond Latch

IP.com Disclosure Number: IPCOM000082971D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Nestork, WJ: AUTHOR

Abstract

The circuit shown was designed to be used in conjunction with high-speed logic circuits. In order to further enhance performance, it is intended for use at a high level of integration in order to minimize load and line capacitances.

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Subnanosecond Latch

The circuit shown was designed to be used in conjunction with high-speed logic circuits. In order to further enhance performance, it is intended for use at a high level of integration in order to minimize load and line capacitances.

The circuit provides a single-level latch function whose output is "in phase" with the input data. In addition, transistor T1 has its base lead to a trilevel control line which allows not only the normal set and reset operations, but also provides for a block/check condition which permits the output to be placed at a positive level, thus effectively blocking input data, while at the same time allowing the output to be used for testing and diagnostic purposes.

The operation is as follows: If the base input to T1 is in a reset mode, (a positive voltage greater than the forward voltage of SD2 output clamp) T1 will be placed into conduction and T2 will be turned off. The output of the circuit will then be at a down level. When the reset line is dropped to ground, the circuit is ready to accept input data. If the input is at a down level, no change in state will occur; however, if the input is at a plus or up level, SD1 will be placed into forward conduction, transistor T1 will be turned off, transistor T2 will be turned on, and the output will be at a positive level. By virtue of the feedback from the output to the base of T2, the circuit will now stay in a latched condition.

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