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Computer Reliability Predictions

IP.com Disclosure Number: IPCOM000082976D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Westcott, DW: AUTHOR

Abstract

In a computer, the memory is normally more than 90% of the equivalent gates. Thus, a prediction of the memory's reliability is an accurate prediction of the central processing unit's (CPUs) reliability.

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Computer Reliability Predictions

In a computer, the memory is normally more than 90% of the equivalent gates. Thus, a prediction of the memory's reliability is an accurate prediction of the central processing unit's (CPUs) reliability.

In this description, each time the error correcting circuits (ECC) make a correction, the address and error bits are stored in a separate error recording memory area. The operating system (OS) program is used to compare accumulated error data from the ECC correction from a predetermined error occurrence pattern, ultimately generating a request for the customer engineer (CE), which is typed out at the operator console.

The difference between this method and the present method is that IBM 370 systems with ECC capabilities use a "hog-out" system. The log-out system records intermittent problems as they occur and then lists the error's address and bit location in a hard-copy print-out, but the print-out is obtained only when the CE requests the log out for a planned diagnostic, whereas in this method a request for the CE is printed out at the operator's console because of the predetermined error occurrence pattern.

The ECC raises a line when an error is detected and the error is either corrected or indicated as a double error. The error detection line causes a branch in the microcode to trigger a disc address stored in the machine register and stores and "jailed" address and bit locations. At the same time, the error detection line set...