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Moving Register Bits Under Masks

IP.com Disclosure Number: IPCOM000082979D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Ossolinski, EJ: AUTHOR [+3]

Abstract

This is a technique for moving register bits under masks. The large number of combinatorial logic circuits conventionally required to perform the present operation is significantly reduced.

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Moving Register Bits Under Masks

This is a technique for moving register bits under masks. The large number of combinatorial logic circuits conventionally required to perform the present operation is significantly reduced.

Bits in a byte register R2 that are masked by 1's in a mask register M@, replace in order the bits in a byte register R1 that are masked by 1's in a mask register M1. The hardware includes counters to examine the bits in the bytes one at a time and two intermediate registers H2 and H1. H2 is used to compress the R2 bits masked by M2, and H1 is used to form the result from the R1 bits that are unmasked by M1 or the H2 bits (in order) for the R1 bits that are masked by M1. The configuration of counters and registers are shown in Fig. 1 and an example for specific bits is shown in Fig. 2.

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