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Integrated Circuit Latch

IP.com Disclosure Number: IPCOM000082984D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Dansky, AH: AUTHOR [+2]

Abstract

Integrated circuit area is significantly reduced by using single transistors in an AND-INVERT (AI) cell to perform AOI logic.

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Integrated Circuit Latch

Integrated circuit area is significantly reduced by using single transistors in an AND-INVERT (AI) cell to perform AOI logic.

Fig. 1 illustrates a typical latch 2 implemented by AND-INVERT logic blocks
4. Presently known AI logic blocks typically require two transistors to perform the desired circuit function. For example, the two inputs to a two-legged AI logic block are connected to the emitters of a multi-emitter transistor, while the collector of the multi-emitter transistor is connected to the base of a second transistor providing an inverted output at its collector.

In order to provide the desired function with significantly less semi-conductor area, the circuit of Fig. 2 is provided. A single transistor such as T1 accomplishes the function of a two-legged AI logic block 4. For example, if a first input terminal B is at a logical uplevel a second input terminal 40 is at a downlevel, the output at the collector of T1 will be at a downlevel. For all other logical input combinations at the input terminals to T1, the output at its collector is at an uplevel.

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