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Low Power Blended Transistor Logic Circuit

IP.com Disclosure Number: IPCOM000082985D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Henle, RA: AUTHOR [+3]

Abstract

Fig. 1 shows a blended transistor logic circuit that has low-power consumption because of high resistance loads R1 and R2.

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Low Power Blended Transistor Logic Circuit

Fig. 1 shows a blended transistor logic circuit that has low-power consumption because of high resistance loads R1 and R2.

For conventional double-diffusion bipolar transistors (P+ isolation or recessed oxide) there is an N-epitaxial, P-channel depletion field-effect device that is compatible with the process. For epitaxial base bipolar transistors there is a P- epitaxial layer, N-channel depletion field-effect transistor device that is compatible with the process.

In Fig. 1, R1 generally has a higher resistance than R2, because a smaller R2 resistance permits a greater output capability. With N-channel depletion devices, the width-to-length (W/L) R2 power consumption is roughly six times greater than R1's power consumption.

Fig. 2 shows a low-power blended transistor logic (P-channel depletion) field- effect transistor mode and is one way to stop quiescent power in R2. When lines A, B and C are up, T2 is on and R2, R3 and R4 are off. Therefore, a steady current can not flow through T2. The depletion device, when it is off, does not exhibit a sharp cut off, but power is saved with 0.1mW consumption using a 0.2 mil technology.

When one or more inputs A, B or C are down, point E is at a low-voltage level, T2 is off, and one or more of R2, R3 and R4 are on, pulling the output to its most positive level. Again no steady-state current will flow.

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