Browse Prior Art Database

NPN NChannel Bipolar FET Devices

IP.com Disclosure Number: IPCOM000082987D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

The present process provides for the manufacturing of bipolar field effect transistors (BIFET) devices by simultaneously forming NPN bipolar transistors in an epitaxial layer, simultaneously with the formation of a N-channel in the substrate supporting the epitaxial layer. The result is a substantially planarized BIFET structure.

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NPN NChannel Bipolar FET Devices

The present process provides for the manufacturing of bipolar field effect transistors (BIFET) devices by simultaneously forming NPN bipolar transistors in an epitaxial layer, simultaneously with the formation of a N-channel in the substrate supporting the epitaxial layer. The result is a substantially planarized BIFET structure.

With reference to Fig. 1, source and drain 10 and 11 of the FET have been formed in substrate 12, as has subcollector 13 of the bipolar transistor. Ptype epitaxial layer 14 has been grown on the substrate ]2. The substrate is coated with SiO(2) layer 15 which is in turn covered by polysilicon layer 16. Openings 18 and 19 have been formed to the source 10 and drain 11, as has opening 20 through which the emitter will be eventually formed. A silicon nitride layer 17 has been formed over the P epitaxial structure 14.

Next, as shown in Fig. 2, an N+ doped polysilicon layer 21 is deposited in opening 20 simultaneously with the deposition of similar polysilicon layers 22 and 23 in the source and drain, as well as N+ polysilicon layer 24 in the gate region. This deposition of polysilicon is carried out at a low temperature (below 800 degrees C) and a low-deposition rate, in order to ensure the deposition on the exposed silicon epitaxial layer as well as in the gate region. The N+ doped polysilicon may be made by including N dopant within the deposited polysilicon and/or by ion implanting N impurities at low ener...