Browse Prior Art Database

Dual Gate Programmable Logic Array

IP.com Disclosure Number: IPCOM000082998D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kelly, GJ: AUTHOR [+2]

Abstract

The speed performance of a field-effect transistor circuit is directly proportional to the physical area of transistors in the circuit. The figure shows a portion of a field-effect transistor programmable logic array having doubled speed performance without an increase in area.

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Dual Gate Programmable Logic Array

The speed performance of a field-effect transistor circuit is directly proportional to the physical area of transistors in the circuit. The figure shows a portion of a field-effect transistor programmable logic array having doubled speed performance without an increase in area.

The input and output lines on a programmable logic array are usually spaced to allow a device at each intersection, as exemplified by field-effect transistors 17, 21, 23 and 25. In the figure, load or precharge devices 11 connected to array output lines such as lines 13 and 31 provide a signal whenever all intersection transistors connected to a particular array output line are nonconducting, by virtue of the absence of an input signal such as a signal on input line 19, or the absence of a gate connection as exemplified by field-effect transistor 23.

Since field-effect transistor 17 must conduct the current provided by load or precharged device 11, as well as the intrinsic capacitance discharging current from the array output line 13, the internal resistance of device 17 determines how fast array output line 13 will be discharged. The effective size of transistor 17 can be doubled by connecting transistor 21 in parallel with transistor 17, without effecting the size of either transistor or the size of the entire array.

The use of both transistors 17 and 21 at the intersection of data input line 19 and array output line 13 means that adjacent data input li...