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Test Pulse Generator

IP.com Disclosure Number: IPCOM000083009D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Beh, C: AUTHOR [+2]

Abstract

The circuit of Fig. 1 forms the signals of Fig. 2 that are applied to a semiconductor store for testing operations. A pulse generator supplies the signal Pulse at a frequency that is selected to establish the duty cycle for the test. This signal is applied to a monostable circuit 3 that produces at its 1 output the signal Set. The width of signal Set is established by a resistor-capacitor network 17 monostable circuit 3.

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Test Pulse Generator

The circuit of Fig. 1 forms the signals of Fig. 2 that are applied to a semiconductor store for testing operations. A pulse generator supplies the signal Pulse at a frequency that is selected to establish the duty cycle for the test. This signal is applied to a monostable circuit 3 that produces at its 1 output the signal Set. The width of signal Set is established by a resistor-capacitor network 17 monostable circuit 3.

The 1 output of monostable circuit 3 is connected to trigger a second monostable circuit 4 and the output of monostable circuit 4 is connected to trigger a monostable circuit 5. The 1 output of monostable circuit 5 establishes the timing and width of the pulse Sample Reset. The timing of monostable circuit 4 establishes the delay between the rise of the signal Pulse and the rise of Sample Reset.

A gate 6 forms the signal Restart as the OR logic function of the pulse Set and the signal Pulse that is delayed by a chain of amplifiers 7. Thus, Restart rises slightly after Pulse and has a pre-selected width.

The complement Set signal is connected to the trigger input of a circuit 8 that divides the frequency of the pulse generator by two.

The circuit illustrates a variety of pulse forming techniques that can be readily implemented in commercially available integrated circuits. The unused components of the circuits are not shown in the simplified arrangement of Fig. 1.

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