Browse Prior Art Database

Multiple Class Cycle Steal System

IP.com Disclosure Number: IPCOM000083021D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+5]

Abstract

In a stored program computer system, data transfers between the central processing unit or storage and input/output (I/O) devices takes place under cycle steal control, i.e., no instructions required for the data transfers, where the cycle steal mode is structured by class to accommodate different data transfer rate requirements, and thus optimize the data transfer efficiency of the computer system.

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Multiple Class Cycle Steal System

In a stored program computer system, data transfers between the central processing unit or storage and input/output (I/O) devices takes place under cycle steal control, i.e., no instructions required for the data transfers, where the cycle steal mode is structured by class to accommodate different data transfer rate requirements, and thus optimize the data transfer efficiency of the computer system.

There are three classes of cycle steal for controlling the data transfers. Burst mode cycle steal accommodates data transfers for I/O devices having the highest data transfer rate. Expansion cycle steal operates in an allow mode and in a dedicated mode. The allow mode is interleaved with the burst mode and facilitates data transfers at a rate lower than the burst mode. The dedicated mode is next in priority to the burst mode and, when enabled, it facilitates data transfers at rates up to the same rate as the burst mode.

A low performance cycle steal mode has the lowest priority and data transfer rate, but provides cycle steal capability to increase data transfer rates over data transfer rates capable under instruction control. The low performance cycle steal mode utilizes all of the same control logic used for data transfers under instruction control and, therefore, only requires minimal additional control logic to provide the cycle steal capability.

The stored program computer system in Fig. 1 includes storage 10, CPU 11, port cycle steal controls 20, expansion port 40, burst mode attachment 45, I/O device attachment 50 and I/O device attachment 55. An I/O cycle steal device attachment 60 communicates with expansion port 40 and controls I/O cycle steal device 65. A burst mode I/O device 70 is attached to the burst mode attachment 45.

An I/O cycle steal device 75 which, for example, could be a low performance disk drive or any other low performance I/O cycle stealing type of device, is attached to attachment 50 which could also service noncycle steal I/O devices. A noncycle steal I/O device 80 is attached to attachment 55.

Attachment 55 and noncycle steal I/O device 80 are included only for the purpose of illustrating that the same control logic used for data transfers under instruction control, is also used by the low performance I/O cycle steal device attachment 50. When data is transferred under instruction control, the I/O instruction must be fetched from storage 10 and decoded by CPU 11. Port 20 then establishes synchronization between attachment 55 and CPU 11. Thus, data transfers under instruction control consume more time, in view of the time required for instruction fetching and execution. Data transfers under control of attachment 50 for cycle stealing I/O devices are at a faster rate than those under control of attachment 55 for noncycle stealing I/O devices, but at a slower rate than those under control of attachments 45 and 60.

Attachments 45 and 60 must be inactive in order for attachmen...