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Thermal Oxide Isolation Process for High Density Memories

IP.com Disclosure Number: IPCOM000083042D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

In the conventional 5-mask recessed oxide-modified (ROX-MOD) process for 1-device memories, thermal oxide is grown over the poly-Si plate, Si bit line, and Si storage node to electrically isolate the Al word line from the cell (see Figs. 1A and 1B). During this oxide growth, Si in the region of the bit line is consumed (e.g., in growing 3000 angstroms of thermal oxide for isolation, 1350 angstroms of Si are consumed).

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Thermal Oxide Isolation Process for High Density Memories

In the conventional 5-mask recessed oxide-modified (ROX-MOD) process for 1-device memories, thermal oxide is grown over the poly-Si plate, Si bit line, and Si storage node to electrically isolate the Al word line from the cell (see Figs. 1A and 1B). During this oxide growth, Si in the region of the bit line is consumed (e.g., in growing 3000 angstroms of thermal oxide for isolation, 1350 angstroms of Si are consumed).

In order to compensate for this consumption, conventionally deeper bit line implants (or diffusions) are used which, in turn, require deeper recessed oxide isolation regions and thicker poly-Si gate and storage plate regions for implantation masking. All of this leads to an expanded cell area and to several process difficulties, particularly as regards implantation masking.

A method for circumventing the troublesome thermal oxidation consumption of the bit line region is described here. The basic idea is to obtain a structure, as shown in Fig. 1B and 2A, which contains two levels of poly-Si. The thin poly-Si layer (approximately 1350 angstroms) occurs in the regions to be thermally oxidized. All of this thin sacrificial poly-Si layer will be converted to oxide (3000 angstroms), thus preserving the original bit line. Fabrication of a double-level poly-Si structure is a nontrivial matter. Note for example that the bit line and storage node implants must be performed prior to thermally oxidizing the thin poly-Si.

The primary and preferred approach to fabricating the double-level poly-Si structure uses epitaxial poly-Si refill (see Figs. 2A-2C and Refs. 2-4). Two other approaches that might prove feasible are microetching (see Figs. 3A and 3B and Ref. 5) and controlled chemical etching of the thicker poly-Si (see Figs. 3A and 3B). Of these, the poly-Si refill method is preferred because it is possible implant (or diffuse) the bit line and storage node directly into the Si substrate, while with the second and third approache...