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Waveform Monitor Using Josephson Technology

IP.com Disclosure Number: IPCOM000083046D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

Referring to Figs. 1 and 2, there is shown therein a waveform monitoring system and associated waveforms which provides for the accurate monitoring of fast rising and falling current waveforms, resulting from the operation of Josephson junction devices. Known systems presently employed for monitoring waveforms only operate in an increasing current mode, due to latching of the devices involved. At the present time, there is a need to monitor waveforms having rising and falling current components of the type similar to that identified as waveform C in Fig. 2.

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Waveform Monitor Using Josephson Technology

Referring to Figs. 1 and 2, there is shown therein a waveform monitoring system and associated waveforms which provides for the accurate monitoring of fast rising and falling current waveforms, resulting from the operation of Josephson junction devices. Known systems presently employed for monitoring waveforms only operate in an increasing current mode, due to latching of the devices involved. At the present time, there is a need to monitor waveforms having rising and falling current components of the type similar to that identified as waveform C in Fig. 2.

In Fig. 1, G1 to G4 represent latching Josephson logic gates, the gates having the following roles in the circuit.

G1 generates the waveform to be monitored (i(t) or C) at a specific time within the logic cycle, determined in this particular example by the ramp waveform A(t) reaching the point denoted by the cross in Fig. 2.

G2 generates the sampling pulse of amplitude i(o) > i(t), denoted by the waveform D at a specific time determined by when the algebraic sum of the waveform A(t) and a DC or low-frequency bias B(T) exceeds the switching threshold T(G2) of gate G2, i.e., A(t) + B(T) = T(G2) (1)

G3 is the sampling gate which switches to the V does not = 0 state when i(t) + i(o) + K >T(G3) (2) where i(t) is the instantaneous amplitude of the waveform under test, i(o) the amplitude of D, K an externally applied DC bias from DC supply L, and T(G3) the threshold of the gate G3.

G4 is the error detecting gate, which operates with a total control input of F given by F = D-E, where D and E are designed to have the same "zero" (= 0) and "one" ( i(o)) levels.

The circuit operates by automatically adjusting the DC bias K to be proportional to the instantaneous value of the waveform C at the sampling point, correspond...