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Josephson Junction Analog to Digital Converter

IP.com Disclosure Number: IPCOM000083048D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 83K

Publishing Venue

IBM

Related People

Klein, M: AUTHOR

Abstract

Some previous descriptions on analog-to-digital conversion (see references) make use of the gap voltage of a switched Josephson junction as a unit of voltage and a standard. They require in addition, control currents which must be set with some precision. The present description also uses the gap voltage as a unit, but makes only relaxed requirements on precise control currents. It is slower but it can, in principle, be extended to a large number of digits at the cost of time of operation and component count, but without increasing demands for precision of resistors and currents.

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Josephson Junction Analog to Digital Converter

Some previous descriptions on analog-to-digital conversion (see references) make use of the gap voltage of a switched Josephson junction as a unit of voltage and a standard. They require in addition, control currents which must be set with some precision. The present description also uses the gap voltage as a unit, but makes only relaxed requirements on precise control currents. It is slower but it can, in principle, be extended to a large number of digits at the cost of time of operation and component count, but without increasing demands for precision of resistors and currents.

The basic principle used is ramp conversion. This principle is well known (see Ref. 1). Fig. 1 illustrates this principle. A stepped ramp reference signal is continuously compared with the analog input current. When the two signals are detected to be equal, the ramp is interrupted and its level is converted to binary output.

Fig. 2 shows a block diagram of Josephson circuits to accomplish this function. The details of the circuits represented by the blocks are provided in subsequent figures. In Fig. 2, in addition to the analog input signal several other inputs are shown. These are signals that would be provided by the system of which the converter was a part. The reset signal is a DC input which is interrupted at a suitable time by the system. Clock 1 and Clock 2 are two-phase clock signals provided by the system and the start signal is likewise provided by the system. The reset signal is DC until the whole circuit is to be reset at the end of an operating cycle.

A start signal in coincidence with Clock 1 switches junction a to the voltage state. The resulting current together with reset switches junction b. Junction c does not switch immediately because Clock 2 is not present. At Clock 2 time junction c switches, etc. Thus signals appear sequentially and switch Junctions S1, S2, S3, etc., in time sequence.

Fig. 4 shows the ramp generator operated by currents in junctions S1, S2, S3, etc., which were shown in Fig. 3. The sequential signals at S1, S2, S3 switch junctions R1, R2, R3 in sequence. The voltage at point V rises as a stepped ramp, with voltage increments equal to the 2 delta voltage of junctions R1, etc. A current proportional to this voltage is supplied to the comparison junction.

A stop signal, whose origin will be described presently, supplies a control current to all of junctions R preventing them from switching, even though the switches S continue to operate in sequence. The result is that after arrival of the stop signal junctions R1, R2 . . . Rk have been switched to the voltage state, while junctions Rk+1, Rk+2 . . . Rn remain in the superconducting state.

It should be noted that the feature in Fig. 4 of using the sum of the 24 voltages across a string of junctions as a reference voltage, is contained in the cited reference of Herrell and Fang.

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Fig. 5 shows the comparison junc...