Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Performance Interconnection of Josephson Circuit Chips

IP.com Disclosure Number: IPCOM000083064D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Grebe, KR: AUTHOR [+2]

Abstract

Josephson junction logic and memory circuits have intrinsic high-speed capabilities, because signal transmission can be performed in nearly loss-less superconducting transmission lines. In order to keep the high-speed advantage of such circuits, it is necessary that the chip-to-chip interconnections be as short as possible. A very low-cost, high-speed interconnection scheme has been proposed in chip sample holders for planar packaging schemes (see IBM Technical Disclosure Bulletin, Vol. 17, No. 2, July 1974, pp.583-584, by R. S. Warren).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

High Performance Interconnection of Josephson Circuit Chips

Josephson junction logic and memory circuits have intrinsic high-speed capabilities, because signal transmission can be performed in nearly loss-less superconducting transmission lines. In order to keep the high-speed advantage of such circuits, it is necessary that the chip-to-chip interconnections be as short as possible. A very low-cost, high-speed interconnection scheme has been proposed in chip sample holders for planar packaging schemes (see IBM Technical Disclosure Bulletin, Vol. 17, No. 2, July 1974, pp.583-584, by R. S. Warren).

Using the same contact arrangement as is shown in the above-identified publication, a three-dimensional packaging arrangement can be obtained. The packaging arrangement maintains high-speed transmission throughout a plurality of interconnected circuits. It appears to be intrinsically inexpensive and can be fabricated using known techniques. Replacement of single chips and repair of individual contacts can be made with the proposed interconnection arrangement. Free flow of liquid He between chips is possible, and connection to the outside of a dewar with a single sheet of interconnecting material can be achieved.

Referring to Figs. 1A, 1B, circuit interconnections are laid out as lines 1 over groundplane 2 (both made of superconducting metals) onto flexible thin sheet 3. Hole 4 is punched in sheet 3 over which circuit chips 5 are disposed. Lines 1 on flexible interconnection sheet 3 are matched to lines 6 on chip 5 and reinforced by a cushion of contact material 7 in the region of overlap.

Contact material 7 may be made of indium or other soft or low melting point material. Using, for example, H-film*, which is a very stable polymer film, as flexible sheet 3, groundplane 2 is placed on the bottom thereof providing an impedance of 5 ohms with 3 or 1.5 mil wide lines 1 and one mil or one-half mil thick H-film, respectively. Another reason for using H-film is that it maintains its elastic properties at cryogenic temperatures.

Chip 5 is bonded to sheet 3 at contacts 7 as shown in Figs. 1A,1B. Since it is undesirable to have...