Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Two Junction Josephson Tunneling Device Flip Flop Shift Register

IP.com Disclosure Number: IPCOM000083065D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Baechtold, W: AUTHOR [+2]

Abstract

A two-junction flip-flop previously proposed by W. Baechtold (Fig. 1) consists of two series connected Josephson tunneling devices J1,J2 across a voltage V(G), source shunted with proper load resistors, RL. The basic principle of the circuit operation is that by selecting the proper voltage source and load resistor values, only one Josephson device will be in the "single-particle tunneling" state while the other tunneling device is in the "pair-tunneling" state or vice versa. The stable states define the two logic states of the flip-flop of Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Two Junction Josephson Tunneling Device Flip Flop Shift Register

A two-junction flip-flop previously proposed by W. Baechtold (Fig. 1) consists of two series connected Josephson tunneling devices J1,J2 across a voltage V(G), source shunted with proper load resistors, RL. The basic principle of the circuit operation is that by selecting the proper voltage source and load resistor values, only one Josephson device will be in the "single-particle tunneling" state while the other tunneling device is in the "pair-tunneling" state or vice versa. The stable states define the two logic states of the flip-flop of Fig. 1.

A shift register can be formed with the type of flip-flop shown in Fig. 1. As an illustration, a two-phase master-slave shift register is shown in Fig. 2. The operation of the shift register shown in Fig. 2 can be briefly explained as follows:

1. Neither of devices Q1,Q2 will switch from the pair-tunneling state unless both an input current and a control current are applied. For example, Q1 will not switch unless both I(in) and phi1 are applied simultaneously.

2. Assume initially that Q1 and Q3 are in the pair-tunneling (or "0", state and that Q2 and Q4 are in the single-particle tunneling (or "1", state. Under these circumstances, the shift register is in a 0 logic state.

3. During T1 period as shown in Fig. 3, phi1 is applied. Assume that I(in) is present and that I(in) = 0. Device Q1 then switches to a 1 state forcing Q2 into a 0 state. This new state...