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Josephson Junction Shift Register

IP.com Disclosure Number: IPCOM000083066D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 49K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

The shift register of this description is based on the flip-flop of Fig. 1. Assuming no current flowing initially, then an externally applied DC current, I(dc), applied across A,B splits into the two branches containing Josephson devices J1 and J2, respectively, according to their relative inductances. In general, I(dc) is chosen to be below I(m)(0) of either of the Josephson junctions, J1 and J2, where I(m)(0) is the maximum zero field Josephson supercurrent that either of the junctions can support.

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Page 1 of 4

Josephson Junction Shift Register

The shift register of this description is based on the flip-flop of Fig. 1. Assuming no current flowing initially, then an externally applied DC current, I(dc), applied across A,B splits into the two branches containing Josephson devices J1 and J2, respectively, according to their relative inductances. In general, I(dc) is chosen to be below I(m)(0) of either of the Josephson junctions, J1 and J2, where I(m)(0) is the maximum zero field Josephson supercurrent that either of the junctions can support.

Applying a control current via control line C1 over junction J1 sufficient to suppress I(max) below the DC current flowing through the branch containing J1, results in J1 switching to the finite voltage state. All the externally applied current, I(dc), is then transferred to the right-hand branch containing J2. Once the current in the left-hand branch falls below the minimum holding current, I(min), J1 reverts back to the zero voltage state. The situation after such a set up cycle is be shown in Fig. 2. Generally, I(min) << I(dc) and, for the present purposes, can be neglected.

The current may now be switched from the right-hand branch containing J2 to the left-hand branch containing J1 by the applications of the necessary control current to C2. This is the basic flip-flop action.

For a shift register, such flip-flops are connected, for example, in a fashion such that the current transfer across the loop containing J1 and J2 is controlled by the data present in the previous stage of the shift register, in conjunction with a timing pulse to control the speed of propagation of the data through the shift register. This can be achieved as follows:

Consider the flip-flop of Fig. 3. Each of the junctions J1,J2 now has two control lines. The gain curve and other junction parameters are chosen such that each junction acts as an AND gate. The control lines over the left-hand junction are connected to the data and strobe signals, where "data" represents the data of the previous stage and the strobe is the main timing pulse (the only timing pulse). The right-hand junction has control of not data (data) and the strobe.

For this shift register, a 0 is considered as 0 current while a 1 is a current of amplitude I(dc).

The shift register cell obeys the following truth table. I(dc)

I(dc) strobe data data in left in right 0 1 0 x x 0 0 1 x x 1 1 0 0 1 1 0 1 1 0. where x corresponds to a don't care state.

Thus, a stored 1 corresponds to I(dc) flowing through J2, whereas a 0 corresponds to I(dc) flowing through J1.

1

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A number of the basic cells of Fig. 3 may be interconnected to form an n-bit shift register as depicted in Fig. 4. Note that junctions J1 and J2 of each cell, other than the first cell, have as controls the strobe and the branch containing J2 and J1 of the previous stage, respectively. This is how the data and not data (data) information is conveyed from one cell to the next.

In order that a rac...