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Task Switching

IP.com Disclosure Number: IPCOM000083071D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Chow, CK: AUTHOR

Abstract

The general trend for memory systems in information processing is toward increasing use of hierarchies. A linear hierarchy consisting of n levels of memories, M(1),M(2), ..., M(n), in cascade is shown in the Figure. Generally, the lower the number of the level (or the higher the level), the faster its speed, the higher the cost per byte and the smaller its capacity.

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Task Switching

The general trend for memory systems in information processing is toward increasing use of hierarchies. A linear hierarchy consisting of n levels of memories, M(1),M(2), ..., M(n), in cascade is shown in the Figure. Generally, the lower the number of the level (or the higher the level), the faster its speed, the higher the cost per byte and the smaller its capacity.

One of the important functions of the automatic memory management in a multiprogramming environment is to allow the CPU to switch from task-to-task, in order to achieve good utilization of the resources. Typically, a given task is allowed to execute until it requires information from the lower (i.e., slower) levels. While this information is being transferred from the backing store or the lower level, to the buffer or the highest level, the CPU performs a task switch and starts execution of another task which references only the higher levels of the memory hierarchy.

The crucial problem in task switching is to determine when, or at which level of the memory hierarchy, the task should be switched. The herein described algorithm provides a means for automatically determining the point of task switching, in order to maximize the expected number of successful memory references per unit time. The optimal switching point depends upon the memory hit characteristics of the task, the device access times and the overhead time for performing the task switch.

Let t(1), t(2), ..., t(n) denote, respectively, the device access times of the memories M(...