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Algorithm for Processing of Field Effect Transistor Devices in a Network Analysis Program

IP.com Disclosure Number: IPCOM000083082D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Brennan, PA: AUTHOR [+4]

Abstract

The computer analysis and design of integrated field-effect transistor (FET) circuits is essential for the establishment of a new technology. This task can be accomplished in a fast and efficient way in an interactive circuit design (ICD) environment [1]. The static and dynamic behavior of the circuits are simulated and appropriate design parameters are adjusted to achieve the desired characteristics in a matter of hours, instead of days or weeks. One of the contributing factors to this is the algorithm described below, which improves the convergence properties for the solution of the nonlinear equations and reduces the number of iterations required.

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Algorithm for Processing of Field Effect Transistor Devices in a Network Analysis Program

The computer analysis and design of integrated field-effect transistor (FET) circuits is essential for the establishment of a new technology. This task can be accomplished in a fast and efficient way in an interactive circuit design (ICD) environment [1]. The static and dynamic behavior of the circuits are simulated and appropriate design parameters are adjusted to achieve the desired characteristics in a matter of hours, instead of days or weeks. One of the contributing factors to this is the algorithm described below, which improves the convergence properties for the solution of the nonlinear equations and reduces the number of iterations required.

FET's are high-impedance devices and they behave as open circuits during the start of the DC analysis when all the voltages are low. Due to this property, a straightforward implementation of the Newton iteration scheme [2] either leads to very slow convergence or the convergence may fail to be achieved.

In an algorithm [3] suggested previously, an attempt has been made to "connect" the FET devices to the rest of the circuit during the DC analysis by using four resistors (see Fig. 1). Specifically, two 10(Omega or kOmega) resistors are connected from the source and the drain to the substrate, and two 10/15/ resistors are connected from the source and the drain to the gate.

This approach does improve the convergence properties of computer programs in which it is implemented. However, the convergence may still be slow and may fail to converge, especially when constant-current sources are used in the circuit to drive the FET devices. Further, those four resistors introduce additional nonzeros in the circuit matrix and, therefore, decreases its sparsity and correspondingly increase the computation time and the storage requirements. The resistors approximately double the number of nonzeros, compared with those introduced by the device alone.

In the ICD program, the resistors are introduced in a different manner. As shown in Fig. 2, two pairs of resistors, each pair consisting of a large resistor R1 = 10/9/ and a small resistor R2 = 3 are connected from the source to the ground, and from the drain to the ground. The switches, which are in series with re...