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Determining the Optimum Capacity of a Cache Memory

IP.com Disclosure Number: IPCOM000083096D
Original Publication Date: 1975-Mar-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Chow, CK: AUTHOR

Abstract

A method of determining the optimum size of a cache memory as a function of the access time of the cache, the total cost of the hierarchy storage, and other technological parameters is described.

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Determining the Optimum Capacity of a Cache Memory

A method of determining the optimum size of a cache memory as a function of the access time of the cache, the total cost of the hierarchy storage, and other technological parameters is described.

The general trend in the development of large computer systems is toward increasing the use of storage hierarchies. The use of cache memories (in Systems IBM 360 and 370) enhances the performance of large systems. An important problem in design of large systems and or storage hierarchies is to determine the capacity of the cache memory.

The cache memory is generally an integral part of the processor, in a form of buffer. The access time, t, of the cache is determined by the processor speed, since both the cache and processor usually employ the same technology and there is a need to match the cache access time to the processor speed. Hence, the remaining key design parameter is the capacity of the cache memory.

This description provides a means to determine the capacity C of the cache memory. The objective is to minimize the effective storage hierarchy access time, subject to a cost constraint that the total storage hierarchy (including the cache) does not exceed a given cost S(0). The algorithm makes use of the memory miss ratio characteristic exponent alpha and technology cost characteristic exponent beta; and the member of the memory levels, n, in the hierarchy. Input-Parameters The input design parameters are: 1. The...