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Clock Power Optimization

IP.com Disclosure Number: IPCOM000083104D
Publication Date: 2005-Feb-28
Document File: 3 page(s) / 93K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to achieve optimal clock power, and can be deployed or integrated with any placement and optimization tool or methodology. Benefits include greatly improving dynamic power optimization.

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Clock Power Optimization

Disclosed is a method to achieve optimal clock power, and can be deployed or integrated with any placement and optimization tool or methodology. Benefits include greatly improving dynamic power optimization.

Background

High-performance VLSI designs demand optimal power consumption. As more and more silicon is able to fit both desktop and mobile needs, power becomes a crucial factor. Current day auto placers offer only timing-driven and congestion-driven placement techniques; there are few placers which attempt to optimize placement for power. The few tools available on the market that optimize for power use techniques such as sizing, logic restructuring, the effective use of mult-vt and multi-vdd cells, and pin swapping. However, though the clock contributes to 50% of power consumption, none of the current day tools address this issue.

General Description

The disclosed method uses clock power optimization (CPO), a systematic method to achieve optimal clock power that can be deployed or integrated with any placement and optimization tool or methodology. While current methods of optimizing power tend to have a negative impact on performance, CPO is a breakthrough in achieving power optimization while maintaining  performance. Figure 1 shows the current state of the art grouping, and Figure 2 shows the  sequentials grouped and bounded together. The following are the steps for creating the
disclosed method:

1.      Synthesize a fub to achieve good timing results, then merge the clock tree.

a.       When the RTL coder is writing the RTL, he/she instantiates clock macros which drive sequentials.

b.      Merging enables better automatic grouping during placement.

2.      Complete a detailed placement of the design.

3.      Complete a placement grouping on the sequentials cells. The group’s splitting algorithm accomplishes the following:

a.       Divides all the fub sequential cells into separate groups, each identified by their clock net driver.

b.      If a group contains more then the maximum number of elements (this can be defined by the maximum fan-out, or the cap a clock buffer in the design library can drive) it will be divided into two sub groups according to the sequential’s original placement, until the groups fit the sequentials maximum number limit.

c.       If a group contain less then the seque...