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Readback Circuits for Digital Data Recorders

IP.com Disclosure Number: IPCOM000083106D
Original Publication Date: 1975-Apr-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Ottesen, HH: AUTHOR

Abstract

In the circuit illustrated in Fig. 1, signals recorded on magnetic medium 10 are sensed by a read head or transducer 11 and supplied through a preamplifier 12 to a set of digital signal processing circuits. Sample and hold circuit 14 receives a periodic readback signal and samples it at the zero-axis crossing and at the midpoint between zero-axis crossings, as shown in the timing diagram of Fig. 2. These sample and hold signal amplitudes drive analog-to-digital converter (ADC) 15, in which the signal amplitudes are quantized into a set of four digital signals. This set of four digital signals transfers in parallel into a holding register 17, under control of a timing signal received over line 16.

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Readback Circuits for Digital Data Recorders

In the circuit illustrated in Fig. 1, signals recorded on magnetic medium 10 are sensed by a read head or transducer 11 and supplied through a preamplifier 12 to a set of digital signal processing circuits. Sample and hold circuit 14 receives a periodic readback signal and samples it at the zero-axis crossing and at the midpoint between zero-axis crossings, as shown in the timing diagram of Fig. 2. These sample and hold signal amplitudes drive analog-to-digital converter (ADC) 15, in which the signal amplitudes are quantized into a set of four digital signals. This set of four digital signals transfers in parallel into a holding register 17, under control of a timing signal received over line 16.

The output of the holding register 17 drives digital signal processing circuit 18 which equalizes the digital signals. The output set of digital signals from digital signal equalizer 18 is in register 19. Register 19 supplies its set of four digital signals to DC restore circuit 20. DC restore circuit 20 supplies a second set of four digital signals over cable 23 to data detector 24 for synchronous detection of data, as well as to phase error detector circuit 25.

Phase error circuit 25 supplies phase error indicating signals to digital variable-frequency oscillator (VFO) 26. VFO 26 supplies timing signals over line 16 which have a transition at each half period of the bit period for timing the sample and hold circuit 14, ADC 15, gating signals into register 17, plus syn...